Code size: Closing the gap between RISC-V and Arm for embedded applications

One of the issues faced by RISC-V developers is that the code density of the RISC-V instruction set for deeply embedded processors does not match that of Cortex-M with existing tools. That is changing with the product innovations SEGGER have developed, such as the recently-announced SEGGER Linker, capable of reducing code size by up to […]

Profiling and Code coverage on RISC-V using simulation

We recently licensed our Floating point library for RISC-V to a large international corporation. They asked not only for our functional verification suite, but also for a verification of the verification suite. A code coverage report showing that the entire code had been executed. While we know that all lines and every instruction have been […]

The Good, The Best, and The Only

In almost any area that invites comparison people want to know: “Who’s the best?” This goes for hotels, restaurants, manufacturers, and certainly sports teams. The embedded world is no exception. Except in the embedded world there is no contest or competition to decide a winner. The Good The embedded industry has a lot of good […]