My previous blog post covered the SEGGER Linker for RISC-V and the benefits provided by enhanced relaxation. This article continues to explore what SEGGER is doing with its linker technology, advancing what is typically possible.
One of the issues faced by RISC-V developers is that the code density of the RISC-V instruction set for deeply embedded processors does not match that of Cortex-M with existing tools. That is changing with the product innovations SEGGER have developed, such as the recently-announced SEGGER Linker, capable of reducing code size by up to […]
We recently licensed our Floating point library for RISC-V to a large international corporation. They asked not only for our functional verification suite, but also for a verification of the verification suite. A code coverage report showing that the entire code had been executed. While we know that all lines and every instruction have been […]
In almost any area that invites comparison people want to know: “Who’s the best?” This goes for hotels, restaurants, manufacturers, and certainly sports teams. The embedded world is no exception. Except in the embedded world there is no contest or competition to decide a winner. The Good The embedded industry has a lot of good […]
This Easter Friday, I was surprised to see the message that Express Logic has been acquired by Microsoft. The announcements on the websites of both companies do not disclose too much information on how exactly things will continue to operate, but it seems that Microsoft has bought Express Logic because they want the software as […]
This article covers how SEGGER vastly improved its documentation process by taking control of the tools we use and, in the process, removed reliance on FrameMaker.
Things at SEGGER have been slower for the past three months or so. Or at least it may seem like that from the outside. There are two main reasons for this. First, we had a great summer and vacation season in Germany (as in most of Europe). Secondly, we have been busy planning, supervising construction […]
This is the second in the series of postings that describe the quality processes at SEGGER. This article picks a single design principle from the many we use when developing our software products, one that is deeply rooted.
This is the first post in a series that deal with delivering SEGGER products: how they’re designed, developed, tested, documented, and released.
You have probably seen that SEGGER attended the recent (7th) RISC-V Workshop. There we demonstrated J-Link support for RISC-V cores and Embedded Studio for RISC-V, our professional-grade IDE that (unsurprisingly) targets RISC-V processors. This post offers a personal view on RISC-V and a reflection on the workshop.