In previous blog posts I have described the division algorithms SEGGER implemented in emRun. However, which algorithm is best (in terms of code size, execution speed, or power efficiency) is very dependent on the target instruction set architectue (ISA) and the way the ISA is implemented in silicon. This article explains how we help to […]
This article describes a new capability that I added to SEGGER emRun, now available in Embedded Studio 6, to support real-time dynamic storage allocation. These enhancements were inspired during my development of a chess engine, and I’ll describe some of the engine design and why emRun now offers a new allocator.
In the previous article I presented an algorithm for division by calculating a reciprocal. This article presents a way to calculate the reciprocal, rather than looking it up, trading size of lookup table against speed of calculation.
We’ve explored simple algorithms that develop a quotient one digit at a time: reliable, understandable, but ultimately quite slow. Now it’s time to change up a couple of gears and turbocharge division for speed!
This article will explore the classic division algorithms and how they can be implemented efficiently, in terms of code space and execution time, by exploiting machine features. Don’t expect anything astounding here, the algorithms are classic for a reason: this path is well-trodden.
This is the first in a series of articles that attempt to dispel the mystique around division algorithms. We do this by presenting coded algorithms that correctly divide, and describe how variations of these algorithms are used in emRun and emFloat, our C runtime and floating-point libraries.
In recent times, artificial intelligence (AI) and machine learning (ML) have become hot topics, enabling useful applications such as assistive and autonomous driving. Intelligent accessories in the home are now mainstream, employing adaptive audio and acoustic beamforming. This series of articles introduces what’s on the bench at SEGGER Labs…and coming soon.
My previous blog post covered the SEGGER Linker for RISC-V and the benefits provided by enhanced relaxation. This article continues to explore what SEGGER is doing with its linker technology, advancing what is typically possible.
One of the issues faced by RISC-V developers is that the code density of the RISC-V instruction set for deeply embedded processors does not match that of Cortex-M with existing tools. That is changing with the product innovations SEGGER have developed, such as the recently-announced SEGGER Linker, capable of reducing code size by up to […]
This posting continues to explore the performance of floating point and how microcontrollers can efficiently execute basic floating-point operations.