We recently licensed our Floating point library for RISC-V to a large international corporation. They asked not only for our functional verification suite, but also for a verification of the verification suite. A code coverage report showing that the entire code had been executed. While we know that all lines and every instruction have been […]
You have probably seen that SEGGER attended the recent (7th) RISC-V Workshop. There we demonstrated J-Link support for RISC-V cores and Embedded Studio for RISC-V, our professional-grade IDE that (unsurprisingly) targets RISC-V processors. This post offers a personal view on RISC-V and a reflection on the workshop.