RISC-V: Dividing efficiently across different hardware

In previous blog posts I have described the division algorithms SEGGER implemented in emRun. However, which algorithm is best (in terms of code size, execution speed, or power efficiency) is very dependent on the target instruction set architectue (ISA) and the way the ISA is implemented in silicon. This article explains how we help to […]

Size matters – Comparing tool chains and CPUs

Many people think that in today’s world, the size of a program does not matter. In many cases, that is not true, especially in the world of embedded computing systems. I explain why and introduce a benchmark that makes it possible to easily compare the code-size efficiency of different tool chains (Compiler, assembler, linker, run […]