We have been using automated tests on hardware in the Flasher and J-Link departments for some time. But now with the new J-Link PRO PoE, we felt it was time to get some of the evaluation boards out of the cabinets and build a proper test farm. We are selecting the most popular boards so […]
Posts in the Development Tools category:
Debugging with external memory: J-Link adds Dual Memory Maps
The J-Link debug probe does two important things: It downloads programs into RAM or flash memory, and it enables debugging in real time, with the setting of unlimited breakpoints, viewing of memory registers, and much more. Without this debugging ability, we are back to trial and error. When the debug process just stops, with no […]
RISC-V: Dividing efficiently across different hardware
In previous blog posts I have described the division algorithms SEGGER implemented in emRun. However, which algorithm is best (in terms of code size, execution speed, or power efficiency) is very dependent on the target instruction set architectue (ISA) and the way the ISA is implemented in silicon. This article explains how we help to […]
Size matters – Comparing tool chains and CPUs
Many people think that in today’s world, the size of a program does not matter. In many cases, that is not true, especially in the world of embedded computing systems. I explain why and introduce a benchmark that makes it possible to easily compare the code-size efficiency of different tool chains (Compiler, assembler, linker, run […]
Correlating and visualizing data sampling, current consumption, and program execution via Ozone’s Timeline Window
SEGGER’s J-Trace PRO streaming trace probe and Ozone debugger make a great team. One highlight of this symbiotic relationship is the Timeline window. It allows users to correlate and visualize data sampling, current consumption, and program execution in one combined signal plot. This article takes a closer look at this functionality.
Every byte counts – Smallest “Hello world”
When searching on-line for small C-programs, there seems to be a lot of confusion about what is doable and what is not. There are a lot of posts wondering why even for minimal programs such as “Hello world” applications are so big, but not many explanations or fixes. I will show how to make a […]
Debugging the dual-core NXP i.MX RT600 with the one and only SEGGER J-Link
The i.MX RT600 MCU family from NXP is an interesting one. Not only do the i.MX RT600 devices feature a 300-MHz Arm Cortex-M33 processor core, but they also include a 600-MHz Cadence Tensilica HiFi4 DSP processor core. This makes the i.MX RT600 devices very suitable for audio playback and voice user interface applications. However, having […]
Profiling and Code coverage on RISC-V using simulation
We recently licensed our Floating point library for RISC-V to a large international corporation. They asked not only for our functional verification suite, but also for a verification of the verification suite. A code coverage report showing that the entire code had been executed. While we know that all lines and every instruction have been […]
Floating-point face off, part 3: How we do it
This posting continues to explore the performance of floating point and how microcontrollers can efficiently execute basic floating-point operations.
Floating-point face-off, part 2: Comparing performance
I used to think that floating-point was not for Embedded Systems. Too slow, too much code overhead and rounding is always a problem. It turns out that while scaled integers still have a performance benefit, floating-point computations can be done with a surprisingly high performance these days on modern Embedded CPUs. This is true not […]