At SEGGER, we strive to deliver products that make developers go, “Wow!” SEGGER’s J-Link debug probes have an excellent reputation in the embedded industry – the real world full of real people. However, we were still curious to hear what the ever-growing artificial world had to say, so we asked ChatGPT about our market-leading devices. […]
Posts in the J-Link category:
J-Link PRO PoE powers the SEGGER test farm
We have been using automated tests on hardware in the Flasher and J-Link departments for some time. But now with the new J-Link PRO PoE, we felt it was time to get some of the evaluation boards out of the cabinets and build a proper test farm. We are selecting the most popular boards so […]
Debugging with external memory: J-Link adds Dual Memory Maps
J-Link debug probes do two important things: they download programs into RAM or flash memory, and they enable debugging in real time, with the setting of unlimited breakpoints, viewing of memory registers, and much more. Without this debugging ability, we are back to trial and error. When the debug process just stops, with no way […]
CPU Design at SEGGER
CPU design is not normally what we do. But: We actually have 2 CPU designed and in use, an 8-bit and a 32-bit CPU. In this article we look at our 32-bit CPU, or rather how we are creating an enhanced version of it with very high Code Density
Hacking emSecure?
On October 24th of 2021, we were contacted by the Moscow based security company BI.ZONE Research Lab. BI.ZONE is a security research firm, checking software and computer systems for vulnerabilities. They were trying to find weaknesses in J-Link.
Correlating and visualizing data sampling, current consumption, and program execution via Ozone’s Timeline Window
SEGGER’s J-Trace PRO streaming trace probe and Ozone debugger make a great team. One highlight of this symbiotic relationship is the Timeline window. It allows users to correlate and visualize data sampling, current consumption, and program execution in one combined signal plot. This article takes a closer look at this functionality.
Debugging the dual-core NXP i.MX RT600 with the one and only SEGGER J-Link
The i.MX RT600 MCU family from NXP is an interesting one. Not only do the i.MX RT600 devices feature a 300-MHz Arm Cortex-M33 processor core, but they also include a 600-MHz Cadence Tensilica HiFi4 DSP processor core. This makes the i.MX RT600 devices very suitable for audio playback and voice user interface applications. However, having […]
Profiling and Code coverage on RISC-V using simulation
We recently licensed our Floating point library for RISC-V to a large international corporation. They asked not only for our functional verification suite, but also for a verification of the verification suite. A code coverage report showing that the entire code had been executed. While we know that all lines and every instruction have been […]
Finding the right (Q)SPI Flash for your project
Not all SPI Flashes are created equal SPI Flashes have become very popular as an inexpensive way to add nonvolatile storage (flash memory) to an Embedded System. They come in various capacities, so increasing memory is fast and easy. Any microcontroller can interface to them via SPI or QSPI peripheral interfaces, or simple general purpose […]
J-Run: Automating performance tests on real hardware
One of the things that irritates me a lot is manual work that should be automated by machines. Automation always trumps the error-prone human and, in my case, offered the opportunity to get to use some of SEGGER”s software I’d never used before to develop a useful tool.
