You have probably seen that SEGGER attended the recent (7th) RISC-V Workshop. There we demonstrated J-Link support for RISC-V cores and Embedded Studio for RISC-V, our professional-grade IDE that (unsurprisingly) targets RISC-V processors.
This post offers a personal view on RISC-V and a reflection on the workshop.
Was it worth it?
Let’s get this out of the way first. The workshop was an excellent event and I congratulate WDC on the professional way in which it was organised: very impressive and well worth attending! Keynotes and presentation quality were outstanding for the most part, and it was very well attended with over 500 participants.
If you have any interest in RISC-V, this is the event to attend!
The potential for fragmentation
One of the great things about RISC-V is that you are free to add your own instructions set extensions to the core. One of the worst things about RISC-V is that you are free to add your own instruction set extensions to the core.
Yes, it’s that double-edged sword. Adding your own custom instruction set extension means that somebody incurs a cost in the toolset: you would need to add support to the compiler, assembler, possibly the linker, and certainly the debugger. This is where things get to be slightly tricky because absolutely, for sure, toolset software is not the easiest thing in the world to customize.
If you’re doing this in an academic setting, that’s just great, grab toolset sources and tinker away all you like on your favorite Linux!
For a generic or commercial toolset provider, it’s a nightmare. At the workshop we saw two vector extension presentations, for instance. This is not good news for us. The RISC-V Foundation’s vector extension looked a bit tricky to implement in hardware and take advantage of in software. What’s more, Microsemi made the case for mixing cryptographic instructions with the vector register set. This intermingling has immediate repercussions for RTOS and OS vendors alike who must deal with context switches and interrupts in addition to the additional instructions in the toolset.
SEGGER now provide embOS for RISC-V, but for the standard RV32I integer-only instruction set. When RISC-V starts to grow arms and legs, managing the entire tool offering becomes a rather hairy problem. Of course, Arm has been doing this by way of instruction set, profile, and ABI specifications for years, but tool vendors (more than one!) still manage to screw up and produce object code that can’t be linked by “standard checking” tools that enforce object code compatibility. So, what you find is additional switches to relax checking or tools to go and edit the attributes encoded in object files before linking. Fantastic.
Hopefully the young RISC-V Foundation will have the sense to set things in stone relatively quickly. Arm have had a good history in development tool evolution and I wish the RISC-V Foundation all the best in replicating the formal processes that Arm actually manage well in my opinion.
RISC-V adoption
It seems clear that RISC-V now has a lot of interest. And that interest and adoption is driven by the absolute freedom to add instructions to your RISC-V core, something that Arm flat-out forbids (but hey, perhaps an Architectural License allows it). The only addition to the Arm instruction set that doesn’t come from Arm that I know about is Intel’s Wireless MMX, and how popular is that?
The one thing that I took away from the workshop is the ice-cool presentation by WDC that reveals they are going RISC-V throughout the organization, and quitting everything else, and intend to ship two billon RISC-V devices by 2019. Astounding. I believe WDC are using ARC processors in SD cards from their SanDisk acquisition and probably Cortex-R devices in their spinning rust and deep-magic solid state drives. So I guess Arm should be somewhat concerned that the levee is starting to break. And that reminds me, two Arm representatives were at the event.
What next?
It seems clear to me that RISC-V is on an exponential adoption path given the progression in the number of workshop attendees and the quality of the presentations. Following events will be larger, for sure, and SEGGER have plans to attend the next workshop, closer to home, in Barcelona.
We have announced our products for RISC-V and are fully engaged with both the RISC-V Foundation and players in the RISC-V community. You can rely on SEGGER to deliver what you need for your RISC-V projects!
Bootnote
I said it above, I say it again: this is a personal opinion!
